Micrel KSZ8895 Spécifications

KSZ8895MQ/RQ/FMQ Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface Revision 1.7 General Description The KSZ8895MQ/RQ/FMQ i

Micrel, Inc. KSZ8895MQ/RQ/FMQ Register 253 (0xFD): Port 5 Queue 2 Egress Limit Control 3 ...

Micrel, Inc. KSZ8895MQ/RQ/FMQ MIIM Registers All the registers defined in this section can be also accessed via the SPI interface. Note: different ma

Micrel, Inc. KSZ8895MQ/RQ/FMQ MIIM Registers (Continued) Address Name Description Mode Default Register 1h: MII Status 15 T4 Capable 0, No

Micrel, Inc. KSZ8895MQ/RQ/FMQ MIIM Registers (Continued) Address Name Description Mode Default Register 5h: Link Partner Ability 15 Next Pag

Micrel, Inc. KSZ8895MQ/RQ/FMQ MIIM Registers (Continued) Address Name Description Mode Default 1 Remote Loopback 1, Perform Remote loopback,

Micrel, Inc. KSZ8895MQ/RQ/FMQ Absolute Maximum Ratings(1) Supply Voltage (VDDAR, VDDAP, VDDC) ... –0.5V to +2.4V (VDDAT, VDDI

Micrel, Inc. KSZ8895MQ/RQ/FMQ Electrical Characteristics(4, 5) (Continued) VIN = 1.2V/3.3V (typ.); TA = 25°C Symbol Parameter Condition Min. Ty

Micrel, Inc. KSZ8895MQ/RQ/FMQ Timing Diagrams EEPROM Timing Figure 18. EEPROM Interface Input Receive Timing Diagram Figure 19. EEPROM Inter

Micrel, Inc. KSZ8895MQ/RQ/FMQ SNI Timing Figure 20. SNI Input Timing Figure 21. SNI Output Timing Symbol Parameter Min. Typ. Max.

Micrel, Inc. KSZ8895MQ/RQ/FMQ MII Timing Figure 22. MAC Mode MII Timing – Data Received from MII Figure 23. MAC Mode MII Timing – Data Trans

Micrel, Inc. KSZ8895MQ/RQ/FMQ MII Timing (Continued) Figure 24. PHY Mode MII Timing – Data Received from MII Figure 25. PHY Mode MII Timing

Micrel, Inc. KSZ8895MQ/RQ/FMQ List of Figures Figure 1. Broadband Gateway ...

Micrel, Inc. KSZ8895MQ/RQ/FMQ RMII Timing Figure 26. RMII Timing – Data Received from RMII Figure 27. RMII Timing – Data Transmitted to RMI

Micrel, Inc. KSZ8895MQ/RQ/FMQ SPI Timing Figure 28. SPI Input Timing Symbol Parameter Min. Typ. Max. Units fC Clock Frequency 2

Micrel, Inc. KSZ8895MQ/RQ/FMQ SPI Timing (Continued) Figure 29. SPI Output Timing Symbol Parameter Min. Typ. Max. Units fC Clock Freq

Micrel, Inc. KSZ8895MQ/RQ/FMQ Auto-Negotiation Timing Figure 30. Auto-Negotiation Timing Symbols Parameters Min. Typ. Max. Units tBTB FLP

Micrel, Inc. KSZ8895MQ/RQ/FMQ MDC/MDIO Timing Figure 31. MDC/MDIO Timing Timing Parameter Description Min. Typ. Max Unit tP MDC period 400

Micrel, Inc. KSZ8895MQ/RQ/FMQ Reset Timing Figure 32. Reset Timing Symbol Parameter Min. Typ. Max. Units tSR Stable Supply Voltages t

Micrel, Inc. KSZ8895MQ/RQ/FMQ Reset Circuit Diagram Micrel recommends the following discrete reset circuit as shown in Figure 22 when powering up the

Micrel, Inc. KSZ8895MQ/RQ/FMQ Selection of Isolation Transformer(1) One simple 1:1 isolation transformer is needed at the line interface. An isolatio

Micrel, Inc. KSZ8895MQ/RQ/FMQ Package Information(1) 128-Pin PQFP Package Note: 1. Package information is correct as of the publication date. Fo

Micrel, Inc. KSZ8895MQ/RQ/FMQ MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http

Micrel, Inc. KSZ8895MQ/RQ/FMQ List of Tables Table 1. MDI/MDI-X Pin Definitions ...

Micrel, Inc. KSZ8895MQ/RQ/FMQ System Level Applications EthernetMACCPUSwitch ControllerOn-Chip Frame BuffersMII-SW10/100PHY 54-portLANMII-P51-portWAN

Micrel, Inc. KSZ8895MQ/RQ/FMQ Switch ControllerOn-Chip Frame Buffers10/100PHY 55-portLAN10/100MAC 110/100MAC 210/100MAC 310/100MAC 410/100MAC 510/1

Micrel, Inc. KSZ8895MQ/RQ/FMQ Pin Configuration TXM5VDDATFXSD3TXP5333435363738 KSZ8895MQ/RQ/FMQ(Top View)NCPMRXDV/PMCRSDVNCNCNCNCNCNCPWRDN_NINTR_NGND

Micrel, Inc. KSZ8895MQ/RQ/FMQ Pin Description Pin Number Pin Name Type(1) Port Pin Function(2) 1 MDI-XDIS IPD 1 − 5 Disable auto MDI/MDI-X. PD

Micrel, Inc. KSZ8895MQ/RQ/FMQ Pin Description (Continued) Pin Number Pin Name Type(1) Port Pin Function(2) 39 FXSD4 IPD 4 FMQ: Fiber signal d

Micrel, Inc. KSZ8895MQ/RQ/FMQ Pin Description (Continued) Pin Number Pin Name Type(1) Port Pin Function(2) 64 PMRXD1 IPD/O 5 PHY[5] MII/RMII r

Micrel, Inc. KSZ8895MQ/RQ/FMQ Pin Description (Continued) Pin Number Pin Name Type(1) Port Pin Function(2) 78 SMRXC I/O MQ/FMQ: Port 5 Switch

Micrel, Inc. KSZ8895MQ/RQ/FMQ Features Advanced Switch Features • IEEE 802.1q VLAN support for up to 12

Micrel, Inc. KSZ8895MQ/RQ/FMQ Pin Description (Continued) Pin Number Pin Name Type(1) Port Pin Function(2) 86 SCONF1 IPD Pins 91, 86, and 87

Micrel, Inc. KSZ8895MQ/RQ/FMQ Pin Description (Continued) Pin Number Pin Name Type(1) Port Pin Function(2) 100 VDDIO P 3.3V, 2.5V or 1.8V di

Micrel, Inc. KSZ8895MQ/RQ/FMQ Pin Description (Continued) Pin Number Pin Name Type(1) Port Pin Function(2) 113 PS1 IPD Serial bus configurati

Micrel, Inc. KSZ8895MQ/RQ/FMQ Pin for Strap-In Options The KSZ8895MQ/RQ/FMQ can function as a managed switch or an unmanaged switch. If no EEPROM or

Micrel, Inc. KSZ8895MQ/RQ/FMQ Pin for Strap-In Options (Continued) Pin # Pin Name PU/PD(1) Description(1) 83 SMRXD0 IPD/O Switch MII receive bit

Micrel, Inc. KSZ8895MQ/RQ/FMQ Pin for Strap-In Options (Continued) Pin # Pin Name PU/PD(1) Description(1) 101 LED2-2 IPU/O LED2 indicator 2. Str

Micrel, Inc. KSZ8895MQ/RQ/FMQ Introduction The KSZ8895MQ/RQ/FMQ contains five 10/100 physical layer transceivers and five media access control (MAC

Micrel, Inc. KSZ8895MQ/RQ/FMQ PLL Clock Synthesizer The KSZ8895MQ/RQ/FMQ generates 125MHz, 83MHz, 41MHz, 25MHz and 10MHz clocks for system timing.

Micrel, Inc. KSZ8895MQ/RQ/FMQ MDI MDI-X RJ-45 Pins Signals RJ-45 Pins Signals 1 TD+ 1 RD+ 2 TD- 2 RD- 3 RD+ 3 TD+ 6 RD- 6 TD- Table

Micrel, Inc. KSZ8895MQ/RQ/FMQ Crossover Cable A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X dev

Micrel, Inc. KSZ8895MQ/RQ/FMQ Ordering Information Part Number Temperature Range Package Lead Finish/

Micrel, Inc. KSZ8895MQ/RQ/FMQ Figure 8. Auto-Negotiation March 12, 2014 30 Revision 1.7

Micrel, Inc. KSZ8895MQ/RQ/FMQ On-Chip Termination Resistors The KSZ8895MQ/RQ/FMQ reduces the board cost and simplifies the board layout by using

Micrel, Inc. KSZ8895MQ/RQ/FMQ Energy Detect Mode Energy detect mode provides a mechanism to save more power than in the normal operation mode when t

Micrel, Inc. KSZ8895MQ/RQ/FMQ Functional Overview: Switch Core Address Look-Up The internal look-up table stores MAC addresses and their associated i

Micrel, Inc. KSZ8895MQ/RQ/FMQ Inter-Packet Gap (IPG) If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecut

Micrel, Inc. KSZ8895MQ/RQ/FMQ Figure 9. Destination Address Lookup Flow Chart, Stage 1 March 12, 2014 35 Revision 1.7

Micrel, Inc. KSZ8895MQ/RQ/FMQ Figure 10. Destination Address Resolution Flow Chart, Stage 2 March 12, 2014 36 Revision 1.7

Micrel, Inc. KSZ8895MQ/RQ/FMQ The KSZ8895MQ/RQ/FMQ will not forward the following packets: 1. Error packets These include framing errors, Frame Chec

Micrel, Inc. KSZ8895MQ/RQ/FMQ MII Interface Operation The media-independent interface (MII) is specified by the IEEE 802.3 committee and provides a c

Micrel, Inc. KSZ8895MQ/RQ/FMQ Port 5 MAC 5 SW5-MII Interface for the KSZ8895MQ/FMQ Table 4 shows two connection manners: 1. The first is an external

Micrel, Inc. KSZ8895MQ/RQ/FMQ Contents System Level Applications ...

Micrel, Inc. KSZ8895MQ/RQ/FMQ Port 5 MAC 5 Switch SW5-RMII Interface for the KSZ8895RQ The Reduced Media Independent Interface (RMII) specifies a low

Micrel, Inc. KSZ8895MQ/RQ/FMQ SW5-RMII MAC to MAC Connection (‘PHY mode’) SW5-RMII MAC to PHY Connection (‘MAC mode’) External MAC KSZ8895RQ SW5-RM

Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Functionality QoS Priority Support The KSZ8895MQ/RQ/FMQ provides Quality of Service (QoS) for applications suc

Micrel, Inc. KSZ8895MQ/RQ/FMQ The KSZ8895MQ/RQ/FMQ provides the option to insert or remove the priority tagged frame's header at each individu

Micrel, Inc. KSZ8895MQ/RQ/FMQ Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPD

Micrel, Inc. KSZ8895MQ/RQ/FMQ Tail Tagging Mode The Tail Tag is only seen and used by the Port 5 interface, which should be connected to a processor

Micrel, Inc. KSZ8895MQ/RQ/FMQ IGMP Support There are two parts involved to support the Internet Group Management Protocol (IGMP) in Layer 2. The firs

Micrel, Inc. KSZ8895MQ/RQ/FMQ DA found in Static MAC table USE FID Flag? FID Match? DA+FID found in Dynamic MAC table Action No Do Not care Do No

Micrel, Inc. KSZ8895MQ/RQ/FMQ Egress Rate Limit For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for sha

Micrel, Inc. KSZ8895MQ/RQ/FMQ Figure 13. KSZ8895MQ/RQ/FMQ EEPROM Configuration Timing Diagram To configure the KSZ8895MQ/RQ/FMQ with a pre-config

Micrel, Inc. KSZ8895MQ/RQ/FMQ Port 5 PHY 5 P5-MII/RMII Interface ...

Micrel, Inc. KSZ8895MQ/RQ/FMQ To use the KSZ8895MQ/RQ/FMQ SPI: 1. At the board level, connect KSZ8895MQ/RQ/FMQ pins as follows: KSZ8895MQ/RQ/FMQ Pi

Micrel, Inc. KSZ8895MQ/RQ/FMQ SPIQSPICSPIDSPIS_N00000010XA7A6A5A4A3A2A1A0WRITE COMMAND WRITE ADDRESS Byte 1D2D0D1D3D4D5D6D7SPIQSPICSPIDSPIS_ND7 D6 D

Micrel, Inc. KSZ8895MQ/RQ/FMQ MII Management Interface (MIIM) The KSZ8895MQ/RQ/FMQ supports the standard IEEE 802.3 MII Management Interface, also

Micrel, Inc. KSZ8895MQ/RQ/FMQ SMI register Read access is selected when OP Code is set to “10” and bits [2:1] of the PHY address is set to ‘11’. T

Micrel, Inc. KSZ8895MQ/RQ/FMQ Register Description Offset Decimal Hex Description 0−1 0x00-0x01 Chip ID Registers. 2−13 0x02-0x0D Globa

Micrel, Inc. KSZ8895MQ/RQ/FMQ Register Description (Continued) Offset Decimal Hex Description 192−206 0xC0-0xCE Port 2 Control Registers. 2

Micrel, Inc. KSZ8895MQ/RQ/FMQ Global Registers Address Name Description Mode Default Register 0 (0x00): Chip ID0 7−0 Family ID Chip family.

Micrel, Inc. KSZ8895MQ/RQ/FMQ Global Registers (Continued) Address Name Description Mode Default 3 Enable PHY MII/RMII 1, enable PHY P5-MII

Micrel, Inc. KSZ8895MQ/RQ/FMQ Global Registers (Continued) Address Name Description Mode Default 3 Frame Length Field Check 1, will chec

Micrel, Inc. KSZ8895MQ/RQ/FMQ Global Registers (Continued) Address Name Description Mode Default 4 Flow Control and Back Pressure fair

Micrel, Inc. KSZ8895MQ/RQ/FMQ Port Registers ...

Micrel, Inc. KSZ8895MQ/RQ/FMQ Global Registers (Continued) Address Name Description Mode Default 4 Enable Pre-Tag on Switch SW5-MII/RMII Inte

Micrel, Inc. KSZ8895MQ/RQ/FMQ Global Registers (Continued) Address Name Description Mode Default 4 Switch SW5-MII/RMII Speed 1, the switch SW5-M

Micrel, Inc. KSZ8895MQ/RQ/FMQ Global Registers (Continued) Address Name Description Mode Default Register 10 (0x0A): Global Control 8 7−0 Fac

Micrel, Inc. KSZ8895MQ/RQ/FMQ Global Registers (Continued) Address Name Description Mode Default Register 12 (0x0C): Global Control 10 7 Rese

Micrel, Inc. KSZ8895MQ/RQ/FMQ Global Registers (Continued) Address Name Description Mode Default 5 PLL Power Down Pll power down enable: 1 = Ena

Micrel, Inc. KSZ8895MQ/RQ/FMQ Port Registers The following registers are used to enable features that are assigned on a per port basis. The register

Micrel, Inc. KSZ8895MQ/RQ/FMQ Port Registers (Continued) Address Name Description Mode Default 0 Two Queues Split Enable This bit 0 in the reg

Micrel, Inc. KSZ8895MQ/RQ/FMQ Port Registers (Continued) Register 18 (0x12): Port 1 Control 2 Register 34 (0x22): Port 2 Control 2 Register 50 (0x32)

Micrel, Inc. KSZ8895MQ/RQ/FMQ Port Registers (Continued) Register 19 (0x13): Port 1 Control 3 Register 35 (0x23): Port 2 Control 3 Register 51 (0x33)

Micrel, Inc. KSZ8895MQ/RQ/FMQ Port Registers (Continued) Register 25 (0x19): Port 1 Status 0 Register 41 (0x29): Port 2 Status 0 Register 57 (0x39):

Micrel, Inc. KSZ8895MQ/RQ/FMQ Register 60 (0x3C): Port 3 Control 5 ...

Micrel, Inc. KSZ8895MQ/RQ/FMQ Port Registers (Continued) Register 27 (0x1B): Reserved Register 43 (0x2B): Reserved Register 59 (0x3B): Reserved Regis

Micrel, Inc. KSZ8895MQ/RQ/FMQ Port Registers (Continued) Address Name Description Mode Default 4 Advertised Flow Control Capability 1, adver

Micrel, Inc. KSZ8895MQ/RQ/FMQ Port Registers (Continued) Register 30 (0x1E): Port 1 Status 1 Register 46 (0x2E): Port 2 Status 1 Register 62 (0x3E):

Micrel, Inc. KSZ8895MQ/RQ/FMQ Port Registers (Continued) Address Name Description Mode Default 2−0 Port Operation Mode Indication Indicate the

Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Use registers 110 and 111 to read or write data to the static MAC address table,

Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Address Name Description Mode Default Register 112 (0x70): Indirect Data

Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Address Name Description Mode Default 0 Port 1 Interrupt Status 1, Port

Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Address Name Description Mode Default Register 130 (0x82): Global Control 14

Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Address Name Description Mode Default Register 132 (0x84): Global Control

Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Address Name Description Mode Default 4–0 Unknown IP multicast packet for

Micrel, Inc. KSZ8895MQ/RQ/FMQ Register 134 (0x86): Global Control 18 ...

Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Address Name Description Mode Default 1–0 DSCP[1:0] Ipv4 and Ipv6 mappi

Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Register 149 (0x95): TOS Priority Control Register 5 7–6 DSCP[47:46] Ipv4 and

Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Address Name Description Mode Default Register 156 (0x9C): TOS Priority C

Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Address Name Description Mode Default Register 176 (0xB0): Port 1 Control

Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Address Name Description Mode Default Register 177 (0xB1): Port 1 Control

Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Address Name Description Mode Default Register 178 (0xB2): Port 1 Control

Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Address Name Description Mode Default Register 181 (0xB5): Port 1 Control

Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Address Name Description Mode Default Register 183 (0xB7): Port 1 Priorit

Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Address Name Description Mode Default Register 187 (0xBB): Port 1 Queue 0

Micrel, Inc. KSZ8895MQ/RQ/FMQ Advanced Control Registers (Continued) Address Name Description Mode Default Register 190 (0xBE) : Port 1 Queue

Micrel, Inc. KSZ8895MQ/RQ/FMQ Register 181 (0xB5): Port 1 Control 13 ...

Micrel, Inc. KSZ8895MQ/RQ/FMQ Data Rate Selection Table in 100BT Rate for 100BT mode Priority/Queue 0-3 Ingress/egress limit Control Register bit[6:0

Micrel, Inc. KSZ8895MQ/RQ/FMQ Address Name Description Mode Default Register 191(0xBF): Testing Register 7−0 Reserved N/A RO 0x80 Register

Micrel, Inc. KSZ8895MQ/RQ/FMQ Static MAC Address Table KSZ8895MQ/RQ/FMQ has a static and a dynamic address table. When a DA look-up is requested, bot

Micrel, Inc. KSZ8895MQ/RQ/FMQ Examples: (1) Static Address Table Read (read the 2nd entry) Write to Register 110 with 0x10 (read static table select

Micrel, Inc. KSZ8895MQ/RQ/FMQ VLAN Table The VLAN table is used for VLAN table look-up. If 802.1q VLAN mode is enabled (Register 5 bit 7 = 1), this t

Micrel, Inc. KSZ8895MQ/RQ/FMQ Examples: (1) VLAN Table Read (read the VID = 2 entry) Write the indirect control and address registers

Micrel, Inc. KSZ8895MQ/RQ/FMQ Dynamic MAC Address Table This table is read only. The contents are maintained by the KSZ8895MQ/RQ/FMQ only. Address

Micrel, Inc. KSZ8895MQ/RQ/FMQ MIB (Management Information Base) Counters The MIB counters are provided on per port basis. These counters are read usi

Micrel, Inc. KSZ8895MQ/RQ/FMQ For port 2, the base is 0x20, same offset definition (0x20-0x3f) For port 3, the base is 0x40, same offset definition (

Micrel, Inc. KSZ8895MQ/RQ/FMQ The KSZ8895MQ/RQ/FMQ provides a total of 34 MIB counters per port. These counters are used to monitor the port detail a